In designing and manufacturing a chip exemplified by an integrated circuit such as a Large Scale Integration (LSI), a manufactured chip undergoes an error cause analysis and a speed path analysis. The error cause analysis checks a cause of an error, that is, the cause of not increasing the yield of an LSI. The speed path analysis seeks a reason why a time for propagating a signal from an input register to the output register on the actual chip is longer than a time estimated at the designing. Hereinafter, such error cause analysis and speed path analysis may sometimes be collectively called a “failure analysis”.
A general failure analysis is carried out in, for example, the following steps (i) through (iv).
(i) In relation to N (natural number) elements of an actual chip to be designed, estimated values at the designing and measured values on the actual chip are previously derived. Here, representing respective estimated values of elements n (n=1, 2, . . . , N) at the designing by Tdesign(n); respective measured values of the elements n on the actual chip by Tproduct(n); and respective errors (or failure rate or error rate) of the elements n by ε(n), the relationship expressed by the following Formula (1) is established for each element n.Tproduct(n)=Tdesign(n)+ε(n)  (1)
(ii) Assuming candidates for a failure factor to be M (natural number) kinds, the magnitude of influence of m-th factor m (m=1, 2, . . . , and M) of the n-th element n (or the partial circuit n thereof) is derived and is represented by a (m, n).
(iii) A function f (see Formula (2) below) that gives the correlation between a failure factor m and an error ε(n) of each failure element n is derived.ε(n)=f(a(1,n),a(2,n), . . . ,a(M,n))  (2)
The function f is derived through a regression analysis or through machine learning using, for example, a Support Vector Machine (SVM). In a simple case, the function f that uses a magnitude am of influence (an amount of feature) am of each factor m as variables is determined to be the following Formula (3), and weights X1, X2, . . . , Xm, . . . , and XM that provide the best approximations to N ε(n) are derived through a linear regression analysis.f(a1,a2, . . . ,am, . . . ,aM)=a1×X1+a2×X2+ . . . +am×Xm+ . . . +aM×XM  (3)
Specifically, the following simultaneous equations (4-1) through (4-N) are solved through a linear regression analysis to calculate the weights X1, X2, Xm, . . . and, XM.
                              ɛ          ⁡                      (            1            )                          =                                            a              ⁡                              (                                  1                  ,                  1                                )                                      ×            X            ⁢                                                  ⁢            1                    +                                    a              ⁡                              (                                  2                  ,                  1                                )                                      ×            X            ⁢                                                  ⁢            2                    +          …          +                                    a              ⁡                              (                                  m                  ,                  1                                )                                      ×            Xm                    +          …          +                                    a              ⁡                              (                                  M                  ,                  1                                )                                      ×            XM                                              (                  4          ⁢                      -                    ⁢          1                )                                                          ⁢                  ⋮          ⁢                                          ⁢          ⋮                                                                              ɛ          ⁡                      (            n            )                          =                                            a              ⁡                              (                                  1                  ,                  n                                )                                      ×            X            ⁢                                                  ⁢            1                    +                                    a              ⁡                              (                                  2                  ,                  n                                )                                      ×            X            ⁢                                                  ⁢            2                    +          …          +                                    a              ⁡                              (                                  m                  ,                  n                                )                                      ×            Xm                    +          …          +                                    a              ⁡                              (                                  M                  ,                  n                                )                                      ×            XM                                              (                  4          ⁢                      -                    ⁢          n                )                                                          ⁢                  ⋮          ⁢                                          ⁢          ⋮                                                                              ɛ          ⁡                      (            N            )                          =                                            a              ⁡                              (                                  1                  ,                  N                                )                                      ×            X            ⁢                                                  ⁢            1                    +                                    a              ⁡                              (                                  2                  ,                  N                                )                                      ×            X            ⁢                                                  ⁢            2                    +          …          +                                    a              ⁡                              (                                  m                  ,                  N                                )                                      ×            Xm                    +          …          +                                    a              ⁡                              (                                  M                  ,                  N                                )                                      ×            XM                                              (                  4          ⁢                      -                    ⁢          N                )            
The coefficient of a(m, n) in the above Formulae (4-1) through (4-N) represents the value representing a magnitude of influence (an amount of feature) of the factor m on the element n. The value a(m, n) is derived from information of designing the actual chip. Specifically, the value a(m, n) represents a length of wiring on a wiring layer m of a group (partial circuit) n, or the number of cells being used and belonging to a cell type m on an activated path connected to an output register (flip flop) n, as to be detailed below.
(iv) From the form of the function f derived in above step (iii), a factor of the failure is estimated. For example, after the weights X1 through XM are calculated and the function f of Formula (3) is derived, the factor having a weight of the maximum absolute value is estimated to have the largest influence. For example, when the weight Xm has the maximum absolute value, the factor m (the cell type m or the wiring layer m) is estimated to be the cause of the failure.
Next, the error cause analysis and the speed path analysis will now be detailed with reference to FIGS. 13, 14, and 17.
If errors frequently occur in the actual chip, the cause of the failure is checked through the error cause analysis. For example, if a problem arises when the fourth layer is manufactured or a net having a long wiring on the fourth layer has a high error rate, the error cause analysis estimates that the fourth layer (the wiring layer 4) to be the cause of the failure.
In the error cause analysis, nets of the chip are classified into N groups (elements) 1 through N as depicted on the left side of FIG. 13, and the total of wiring length of each wiring layer of each group n is derived as a magnitude a(m, n) of influence (an amount of feature). The error rate ε(n) of each group n is obtained on the basis of the result of measurement on the actual chip. The magnitude a (m, n) of influence and the error rate ε(n) derived in the above manner are applied to Formulae (4-1) through (4-N) to calculate the weights X1 through XM as depicted on the right side of FIG. 13. Apparently from the calculated weights X1 through XM, the weight X4 corresponding to the wiring length of the fourth layer has the maximum absolute value and concurrently exceeds the reference value, and therefore, the wiring layer 4 is estimated to be the cause of the failure.
Otherwise, if a manufactured actual chip does not attain the designed performance, the factor of the failure is checked through the speed path analysis. For example, if cells of a particular cell type have a measured delay value larger than the estimated delay time estimated at designing or a path including many cells of the same cell type has a measured delay value larger than the estimated delay time at designing, the particular cell type is estimated to be a delay factor.
In the speed path analysis, N FF (Flip Flop) elements 1 through N that have measured delay values larger than respective estimated delay value estimated at designing are assumed to be found as depicted in the left side of FIG. 14. To the input side of each FFn, a single activated path n is connected, and the number of cells of the cell type m (Type m) being used on the activated path is derived as a magnitude a(m, n) of influence (an amount of feature). Concurrently, the delay error ε(n) on each FFn (path n) corresponds to the deference between the measured delay value on the actual chip and the estimated delay value at designing. The magnitude a(m, n) and delay error ε(n) derived in the above manner are applied to Formulae (4-1) through (4-N) and thereby the weights X1 through XM are calculated as illustrated in FIG. 17. In the example of FIG. 17, the weights X63, X72, and X153 of cell types f_63, f_72, and f_153, respectively have absolute values exceeding a reference value. The three kinds of cell types f_63, f_72, and f_153 are estimated to be the cause of the failure, i.e., delay.
Next, description will now be made in relation to problems of the error cause analysis and problems of the speed path analysis with reference to FIGS. 15-18.
First, problems of the error cause analysis will be explained. In the example of FIG. 15, the net system is formed by connecting five nets (regions) N1-N5 to one another via four buffers B1-B4. A case is assumed where occurrence of a failure in the net system is acknowledged but the precise position at which the failure is occurring is not acknowledged for the five nets N1-N5. In this case, the candidates (failure candidates) for a region to be specified as the failure occurrence region are the five nets N1 through N5, at least one of which is selected as the group n, which is then subjected to the error cause analysis.
If, for example, the wiring layer 4 is the cause of the failure and each net using the wiring layer 4 in question is selected as the group n among the five nets, the information of the wiring layer 4 is reflected in the result of the error cause analysis and the wiring layer 4 is specified as the cause. Conversely, if a net not using the wiring layer 4 in question is selected as the group n from the five nets, there is a possibility of the error in the result of the analysis. The above error cause analysis does not always output an erroneous result even if one or more of the groups select an incorrect net (i.e., so as not containing the failure wiring layer). However, if an excessive number of groups select incorrect nets, the possibility of error in the result of the analysis is increased to make it impossible to specify the correct failure cause.
Next, problems in the speed path analysis will now be described. In the example of FIG. 16, two activated paths P1 and P2 reach the FFn that occurring delay failure through a two-input one-output gate G. In this case, occurrence of the failure in the FFn is acknowledged by the measured delay value and the estimated delay value estimated at designing, but whether the cause of the delay failure is activated path P1 or P2 is not grasped. So, one of the two activated paths P1 and P2 is selected as the activated path n, which is then subjected to the speed path analysis.
For example, if the activated path P2 is the cause of the delay and the activated path P2 is selected as the path n related to the FFn, the cell information of the activated path P2 and other information are reflected in the result of the speed path analysis, so that a cell type of a cell on the activated path is specified as the cause. Conversely, if the activated path P1 not being the cause of the delay is selected as the path n related to the FFn, there is a possibility of error in the result of the analysis. The above speed path analysis does not always output an erroneous result even if incorrect activated paths are selected for part of the FFs. However, if an excessive number of FFs select incorrect activated paths, the possibility of error in the result of the analysis is increased to make it impossible to specify the correct failure cause.
Here, an example of the result of the speed path analysis will be detailed with reference to FIGS. 17 and 18. FIG. 17 is a diagram illustrating an example of an analysis result when the failure candidates are correctly selected while FIG. 18 is a diagram illustrating an example of an analysis result when the failure candidates are incorrectly selected. FIGS. 17 and 18 concern an experimental example of the speed path analysis in which example three kinds of cell type among about 500 paths are regarded as failure causes and three cell types f_63, f_72, and f_153 are experimented to be detected through the speed path analysis.
FIG. 17 represents an example in which a correct activated path that reaches each FFn is selected as a cause of the delay, in other words, failure candidates are correctly selected. If failure candidates are correctly selected as illustrated in FIG. 17, the absolute values of the weights X63, X72, and X153 of the cell types f_63, f_72, and f_153 exceed a constant value (threshold) and therefore can be estimated to be the causes of the delay.
FIG. 18 represents an example in which a correct activated path that reaches each FFn in not selected as a cause of the delay, in other words, failure candidates are incorrectly selected. If failure candidates are incorrectly selected as illustrated in FIG. 18, the absolute values of weights of many cell types exceed the threshold and therefore the causes the delay are not correctly estimated.    [Patent Literature 1] pamphlet of WO 2004-027440    [Patent Literature 2] Japanese Laid-Open Patent Publication No. HEI 06-083803    [Patent Literature 3] Japanese Laid-Open Patent Publication No. 2000-268073    [Patent Literature 4] Japanese National Publication of International Patent Application No. 2003-524831.